FPGA SDK
Usage
- Do not plug the JTAG with power, this will damage the board
- Burned program blink LED on factory setting, when you power the board, the series LED will blink
- Board support both EPM240T100C5N and EPM570T100C5N
For EPM240T100C5N: PIN37, 39, 88, 90 is for IO For EPM570T100C5N: PIN37, 90 must connect GND, and PIN39, 88 must connect 3v3. And for EPM570T100C5N board, there are four jumpers on the board, please do not remove.
Usage
- Create project
- Create BDF (block diagram / schematic) file
- Verilog file
- Set .v file as symbol
Programming
Programmer - Quartus Prime 16.0 Programmer
- provide power alone, JTAG can not power the target
- programming file support *.sof *.pof *.jam *.jbc *.ekp *.jic
use quartus programmer for EP2C5
upload JIC or SOF file, POF is unsuccessful
Tool Chain
- IDE - QUARTUS II
- Hardware setup - USB Blaster
- programming file .sof
Quartus Use Guidelines
- Setup projects, devices, devices and pin options (unused pins -> all input tri-stated, voltage 3.3V LVTTL)
- Write first Verilog HDL code
- Start -> Start analysis and synthesis (CTRL+K, Processing)
- Netlist reviewers (Tool) -> check RTL viewer
- Pin Plannar (assignment)-> assign pins (CLK_IN -> PIN_J5, LED1 -> PIN_K11, LED2 -> PIN_N15, rst_n_in -> PIN_J9)
- Start Complilation (CTRL+L,Processing)
- Programmer (Tool)
Interface
verilog code
Pin planar, pin assignment
Quartus 11
- Install 11.0_quartus_windows
- Install 11.0_devices_windows -> include only Cyclone II, Max II
Programmer
- Install QuartusProgrammerSetup-16.0.0.211-windows