https://w.electrodragon.com/w/index.php?action=history&feed=atom&title=FPGA_SDK
FPGA SDK - Revision history
2026-07-23T00:05:42Z
Revision history for this page on the wiki
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https://w.electrodragon.com/w/index.php?title=FPGA_SDK&diff=30462&oldid=prev
Chao at 07:40, 7 April 2021
2021-04-07T07:40:50Z
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<p><b>New page</b></p><div><br />
== Usage ==<br />
[[File:EPM570 with jumper.png|thumbnail]]<br />
* Do not plug the JTAG with power, this will damage the board<br />
* Burned program blink LED on factory setting, when you power the board, the series LED will blink<br />
* Board support both EPM240T100C5N and EPM570T100C5N<br />
For EPM240T100C5N: PIN37, 39, 88, 90 is for IO<br />
For EPM570T100C5N: PIN37, 90 must connect GND, and PIN39, 88 must connect 3v3. And for EPM570T100C5N board, there are four jumpers on the board, please do not remove.<br />
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== Usage ==<br />
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[[File:FPGA start.gif|thumb|right]]<br />
* Create project<br />
* Create BDF (block diagram / schematic) file<br />
* Verilog file<br />
* Set .v file as symbol<br><br />
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=== Programming ===<br />
Programmer - Quartus Prime 16.0 Programmer<br />
* provide power alone, JTAG can not power the target<br />
* programming file support *.sof *.pof *.jam *.jbc *.ekp *.jic<br />
<gallery><br />
File:FPGA_programmer.gif | use quartus programmer for EP2C5<br />
File:FPGA_JIC_upload.gif | upload JIC or SOF file, POF is unsuccessful<br />
</gallery><br />
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== Tool Chain ==<br />
* IDE - QUARTUS II <br />
* Hardware setup - USB Blaster<br />
* programming file .sof<br />
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=== Quartus Use Guidelines ===<br />
* Setup projects, devices, devices and pin options (unused pins -> all input tri-stated, voltage 3.3V LVTTL)<br />
* Write first Verilog HDL code<br />
* Start -> Start analysis and synthesis (CTRL+K, Processing)<br />
* Netlist reviewers (Tool) -> check RTL viewer<br />
* Pin Plannar (assignment)-> assign pins (CLK_IN -> PIN_J5, LED1 -> PIN_K11, LED2 -> PIN_N15, rst_n_in -> PIN_J9)<br />
* Start Complilation (CTRL+L,Processing)<br />
* Programmer (Tool)<br />
=== Interface ===<br />
<gallery><br />
File:Verilog_file.png | verilog code <br />
File:Pin_Planar.png | Pin planar, pin assignment <br />
</gallery><br />
=== Quartus 11 ===<br />
* Install 11.0_quartus_windows<br />
* Install 11.0_devices_windows -> include only Cyclone II, Max II<br />
=== Programmer ===<br />
* Install QuartusProgrammerSetup-16.0.0.211-windows<br />
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[[category: FPGA]]</div>
Chao